Due to the demand for increased data storage capacity and density of memory cells of semiconductor memory devices, such devices are being designed with smaller design rules. This demand applies to static random access memory devices (SRAMs), for example, where physical damage and topological miss-alignments in cell areas can generate defective memory cells. Defective or weak memory cells can result in abnormal leakage current flowing through the memory cells during standby states. Efficient and accurate methods for detecting or screening for defective memory cells are important for saving costs of fabrication and testing.
One method that has been proposed for screening for defective memory cells is disclosed, for example, in Japanese Patent Publication No. 1996-312097, and is illustrated in FIG. 1 Referring to FIG. 1, a semiconductor switch 1 is connected between a power supply line Vdd and PMOS transistors M1 and M2 of a SRAM cell. Data is written into the cell when the switch 1 is turned on. The switch 1 is turned off after the writing operation and then returns to a turn-on state after a predetermined time of the turn-off state has elapsed to perform a read operation for the cell. A cell will be deemed to be defective or weak cells if the cell is not successful in reading data after it has been written with the data during the turn-on state of the switch 1.
Another technique to check defective or weak cells is to test performance of data retention in the cell (referred to as “VDR test”) with a power supply voltage. In the VDR test, a modified power supply voltage level of a tester is applied into a SRAM and the data retention capability is verified after an internal power supply voltage level maintains a constant voltage level.
However, the VDR test requires modification of the power supply voltage of the tester, a power recovery time, and a time for settling the internal power supply voltage in the SRAM, which increases the testing time.
Therefore, methods and circuits for effectively and efficiently screening for defective or weak memory cells of a semiconductor memory device are highly desirable.